Shared memory systems are multi-port and categorized as follows:

• UMA (Uniform Memory Access):

  • Shared memory is accessible by all processors through an interconnection network in the same way a single processor accesses its memory.
  • Access Time: Equal for all processors across any memory location.
  • Structure: Centralized memory shared via a single bus or interconnect.
  • Because access to the shared memory is balanced, these systems are called SMP (symmetric multiprocessor)
  • Network can be a single bus, multiple buses, or a crossbar switch
  • Pros/Cons: Easy to program, but limited scalability due to bus bottlenecks.

  

  

• NUMA (Non-Uniform Memory Access):

  • Each processor has part of the shared memory attached.
  • Access Time: Fast for directly attached local memory, slower for remote memory on another node. It depends on the distance to the processor, which results in a non-uniform memory access time.
  • Structure: Memory is physically distributed among processors.
  • Memory has a single address space, any processor could access any memory location directly using its real address.
  • Pros/Cons: Highly scalable, but requires data locality optimization.

• COMA (Cache-Only Memory Architecture):
  • Like NUMA, each processor has part of the shared memory in COMA.
  • Access Time: Dynamic, depending on where the data line currently resides.
  • Structure: No permanent main memory; all memory acts as large local caches (attraction memory) — COMA requires the data to be migrated to the processor requesting it.
  • Pros/Cons: Automatically migrates data to the active core, but requires complex hardware directory tracking.

Shared memory systems can be designed using bus-based or switch-based interconnection networks.

This explains the rules for keeping data synchronized when multiple processors have their own private caches. If one processor changes a variable, the system needs a policy to ensure the other processors do not accidentally use an old, outdated version.

The lecture breaks this down into two distinct categories:

Cache-Memory Coherence (Updating Global Memory)

this handle the choice regarding a process affect on the global memory

• Write-Through: Every time a processor updates its cache, the global memory is updated at the exact same time.
• Write-Back: The cache is updated immediately, but the global memory is only updated much later when that specific block of data needs to be removed (replaced) from the cache to make room for something new.

The Write-Once protocol combines both:

• The very first write to a block uses Write-Through (updating main memory and invalidating other caches).
• All subsequent writes to that same block use Write-Back (updating locally in the cache without touching memory or flooding the bus).
• It strictly uses Write-Invalidate cache-cache coherence.

Cache-Cache Coherence (Handling Other Processors' Caches)

this handle the choice regarding a process affect on another process cache

• Write-Invalidate: Processors can read from their local caches safely until one processor writes new data. When a write occurs, the system marks all copies of that data in other processors' caches as invalid, forcing them to fetch the new version if they need it again.
• Write-Update: When a processor writes new data, it immediately broadcasts that update to all other copies in all other caches to maintain consistency.

Real shared memory systems combine these approaches to maintain overall coherence, resulting in four possible combinations (e.g., Write-Invalidate with Write-Through, or Write-Update with Write-Back)

Some questions may come up to your small brain about consistency at this stage. But don’t worry, dude, we will talk about it in few lines…

Snooping Protocols

Snooping protocols are the actual rulebooks that caches use to keep their data synchronized without needing a central manager.

The core idea is simple: every cache constantly "watches" (snoops on) all the traffic traveling across the shared bus to see what the other processors are doing. Data is moved around in chunks called "blocks," and every block is given a specific State (like a status tag) that dictates what is allowed to happen to it.

These states change dynamically whenever a processor experiences a Read-Hit, Read-Miss, Write-Hit, or Write-Miss.

The lecture outlines five specific snooping protocols: